The present invention relates to integrated circuits. More specifically, the present invention relates to an output buffer having slew rate control.
High-speed data communication circuits frequently use output buffers for transmitting data over transmission media. Electrical signals generated at the outputs of these output buffers can have high slew rates, which can be problematic. Electrical signals with high slew rates tend to radiate excessive electromagnetic energy and contribute to excessive signal reflections, as compared to signals with lower slew rates. Therefore, the slew rate of such an electrical signal should be as slow as possible while still allowing time for the signal to settle to its final value without causing any timing errors.
Existing approaches for adjusting slew rate often use feedback techniques. A buffer""s output is monitored and, through feedback, the signal at the input to the buffer is controlled so as to achieve the desired output slew rate. However, to ensure stable operation, the bandwidth and/or the gain of the feedback loop must be limited. The result is imperfect slew rate control. Another problem is that the devices that are connected to the output signal whose slew rate is being monitored so as to control its slew rate are susceptible to damage from electrostatic discharge.
An output buffer having improved slew rate control is desired.
One aspect of the present invention is directed to a differential output buffer which includes a differential output stage, first and second push-pull circuits and first and second adjustable, controlled current sources. The differential output stage has first and second differential data outputs and first and second output stage control inputs. The first push-pull circuit has first and second complementary data inputs and has an output coupled to the first output stage control input. The second push-pull circuit has first and second complementary data inputs and has an output coupled to the second output stage control input. The outputs of the first and second push-pull circuits have rise times that are controlled by the first controlled current source and fall times that are controlled by the second controlled current source.
Another aspect of the present invention is directed to a differential output buffer which includes a logic high voltage supply terminal for supplying a logic high voltage, a logic low voltage supply terminal for supplying a logic low voltage and first and second complementary data inputs. The output buffer further includes a differential output stage, first and second adjustable controlled current sources and first and second push-pull circuits. The differential output stage has first and second differential data outputs and first and second output stage control inputs. The first push-pull circuit charges a voltage on the first output stage control input toward the logic high voltage with a rise time that is controlled by the first controlled current source and discharges the voltage on the first output stage control input toward the logic low voltage with a fall time that is controlled by the second controlled current source, based on relative logic states of the first and second data inputs. The second push-pull circuit charges a voltage on the second output stage control input toward the logic high voltage with a rise time that is controlled by the first controlled current source and discharges the voltage on the second output stage control input toward the logic low voltage with a fall time that is controlled by the second controlled current source, based on the relative logic states of the first and second data inputs.
Yet another aspect of the present invention is directed to a method of controlling the slew rate at the output of a differential output buffer. The method includes providing a differential transistor pair between first and second differential data outputs and a tail current source, wherein the differential transistor pair has first and second output control inputs, and receives first and second complementary data inputs. The first and second output control inputs are driven between a logic high voltage level and a logic low voltage level with a rise time controlled by a first adjustable controlled current source and a fall time controlled by a second adjustable controlled current source, based on relative logic states of the first and second data inputs.